1. Field of the Invention
The present invention relates to multilayered printed circuit boards including semiconductor integrated circuits (IC/LSI) and bypass capacitors.
2. Description of the Related Art
Recently, higher functionality has been required for electronic devices, and thus higher integration and higher processing speed of a semiconductor integrated circuit (IC/LSI), for example, an application specific integrated circuit (ASIC), mounted on a printed circuit board, have been developed to meet this requirement.
However, on the other hand, higher integration and higher processing speed of a semiconductor integrated circuit cause changes in power supply and ground potential, radiated noise, or the like, which leads to serious problems, for example, an adverse effect on other electronic devices and malfunction of the circuit itself. That is to say, a semiconductor integrated circuit requires a large current due to higher integration, and thus small inductance in a power supply pattern in a printed circuit board causes a large change in power supply voltage. Moreover, radiated noise is caused by changes in power supply and ground potential of a semiconductor integrated circuit, a change in common mode voltage to which the changes in power supply and ground potential are converted on a printed circuit board, and the like.
To solve these problems, hereto, a bypass capacitor has been located near an integrated circuit. A bypass capacitor is a capacitor serving as a virtual power supply that supplies electrical charge to an integrated circuit from the vicinity of the integrated circuit.
According to the disclosure in Japanese Patent Laid-Open No. 9-139573, bypass capacitors are located as close to power supply terminals of integrated circuits as possible, and radiated noise is suppressed by providing inductances between main power supply wiring and the integrated circuits.
Moreover, recently, semiconductor packages including several hundreds of pins, for example, a ball grid array (BGA) and a quad flat package (QFP), have been used. A large portion of the area around such a semiconductor package is occupied by lead-out signal lines, and it is difficult to install the power supply wiring pattern disclosed in the document described above. Thus, a multilayered printed circuit board as shown in FIG. 9 is used. In this multilayered printed circuit board, power supply wiring extends through a via hole (a through hole) to the back face of the printed circuit board, and a bypass capacitor is mounted on the back face of the printed circuit board.
In FIG. 9, the multilayered printed circuit board includes an integrated circuit (IC) 101 that generates noise, a power supply terminal 102 that supplies power to the IC 101, a ground terminal 103 that supplies a reference potential to the IC 101, and I/O terminals 104 having predetermined functions for the IC 101. The printed circuit board further includes a first surface-layer conductor 105 on which the IC 101 is mounted, first power supply wiring 106 installed in the first surface-layer conductor 105, and an inner-layer ground conductor 107. The printed circuit board further includes an inner-layer main power supply plane 108 that constitutes a power supply system of the printed circuit board and a second surface-layer conductor 109 on a face of the printed circuit board opposite to a face of the printed circuit board on which the first surface-layer conductor 105 is provided. The printed circuit board further includes a power-supply via hole (a through hole) 110 that extends from the first surface-layer conductor 105 to the second surface-layer conductor 109 and that connects to the inner-layer main power supply plane 108, and second power supply wiring 111 that extends to the second surface-layer conductor 109 out of the power-supply via hole 110. The printed circuit board further includes a bypass capacitor 112 mounted on the second surface-layer conductor 109, and a ground via hole 113 that constitutes the shortest path for a current through the bypass capacitor 112 to go back to the ground terminal 103. Although the bypass capacitor 112 is actually disposed on the back face of the second surface-layer conductor 109, the bypass capacitor 112 is disposed on the front face of the second surface-layer conductor 109 in FIG. 9 for the sake of simplifying the illustration.
An ideal bypass capacitor has characteristics such that the impedance decreases as the frequency increases. However, an actual capacitor has impedance characteristics of an equivalent circuit represented by an inductance-capacitance-resistance (LCR) series circuit, as shown in FIG. 10, because a parasitic inductance, a parasitic resistance, and the like are generated. FIG. 10 shows impedance characteristics of a bypass capacitor having a capacitance value of 0.1 μF. The parasitic inductance of a ceramic chip capacitor ranges from about 0.5 to 1.5 nH, and the resonant frequency of a bypass capacitor that has a capacitance value of 0.1 μF, which is often used, is more than 10 Mhz.
Accordingly, at operating clock frequencies of recent integrated circuits and in a critical frequency domain (from 30 MHz) in radiated noise, a bypass capacitor can be considered as an inductive low-impedance element. That is to say, the impedance value in a target frequency band is determined by the inductance value. Moreover, the noise reduction effect of a bypass capacitor is actually determined by impedance characteristics including the inductance of wiring between a power supply terminal of an integrated circuit and a bypass capacitor.
However, in the structure shown in FIG. 9, a noise current generated by the operation of the IC 101 flows from the power supply terminal 102 to the power-supply via hole 110 through the first power supply wiring 106. Then, at the intersection point of the power-supply via hole 110 and the inner-layer main power supply plane 108, the noise current branches off to the inner-layer main power supply plane 108 and the bypass capacitor 112 in proportion to their impedance ratio.
In this structure, the parasitic inductance (equivalent series inductance (ESL)) of the bypass capacitor and inductances of the second power supply wiring 111 and the power-supply via hole 110 are provided between the bypass capacitor 112 and the IC 101. Thus, the impedance between the bypass capacitor 112 and the IC 101 is higher than the impedance between the inner-layer main power supply plane 108 and the IC 101, and the current flows into the inner-layer main power supply plane 108, which is likely to serve as an antenna. Accordingly, radiated noise is not effectively suppressed by the bypass capacitor 112.